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HD151BF854
2.5 V PLL Clock Buffer for DDR Application
ADE-205-696D (Z) Preliminary Rev.4 Jan. 2003 Description
The HD151BF854 is a high-performance, low-skew, low-jitter, PLL clock buffer. It is specifically designed for use with DDR (Double Data Rate) PC mother board application.
Features
* * * * * *
*
Designed for DDR200/266/333/400 PC mother board clock buffering Supports 60 MHz to 210 MHz operation range Distributes one to six differential clock outputs pairs Spread spectrum clock compatible External feedback pin (FBIN) is used to synchronize the outputs to the clock input Supports 2.5 V analog supply voltage (AVDD), and 2.5 V VDD Ordering Information
Package Type SSOP-28 pin Package Code SSOP-28 Package Abbreviation SS Taping Abbreviation (Quantity) EL (1,000 pcs / Reel)
Part Name HD151BF854SSEL
Note: Please consult the sales office for the above package availability.
HD151BF854
Key Specifications
* Supply voltages: VDD = AVDD = 2.5 V0.2 V * Output clock cycle to cycle jitter = 75 ps * Output clock pin to pin skew = 150 ps
Function Table
Inputs AVDD GND GND 2.5 V (typ.) 2.5 V (typ.) H: High level L: Low level CLK L H L H Outputs Yn L H L H Yn H L H L FBOUT L H L H PLL Bypass / Off Bypass / Off Running Running
Rev.4, Jan. 2003, page 2 of 11
HD151BF854
Pin Arrangement
Y0 1 Y0 2 VDD 3 Y1 4 Y1 5 GND 6 NC 7 CLKIN 8 NC 9 AVDD 10 AGND 11 VDD 12 Y2 13 Y2 14
28 GND 27 Y5 26 Y5 25 Y4 24 Y4 23 VDD 22 NC 21 NC 20 FBIN 19 FBOUT 18 NC 17 Y3 16 Y3 15 GND
(Top view)
Rev.4, Jan. 2003, page 3 of 11
HD151BF854
Pin Functions
Pin name AGND AVDD No. 11 10 Type Ground Power Description Analog ground. AGND provides the ground reference for the analog circuitry. Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Clock input. CLKIN provides the clock signal to be distributed by the HD151BF854 clock buffer. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLKIN and FBIN so that there is nominally zero phase error between CLKIN and FBIN. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Ground Power supply Clock outputs. (+Clock) These outputs provide low-skew copies of CLK. Bar clock outputs. (-Clock) These outputs provide low-skew copies of CLK. Don't connect any VDD or GND.
CLKIN
8
Input
FBIN
20
Input
FBOUT
19
Output
GND VDD Y Y NC
6, 15, 28 3, 12, 23 2, 4, 13, 17, 24, 26 1, 5, 14, 16, 25, 27
Ground Power Output Output
7, 9, 18, 21, NC 22
Rev.4, Jan. 2003, page 4 of 11
HD151BF854
Logic Diagram
2 1 10
Y0 Y0
AVDD
Test Logic
4 5
Y1 Y1
13 14
Y2 Y2
17 16
Y3 Y3
24 25
Y4 Y4
CLKIN
8
PLL
26 27
Y5 Y5
FBIN
20
19
FBOUT
Note: All inputs and outputs are associated with VDDQ = 2.5 V.
Rev.4, Jan. 2003, page 5 of 11
HD151BF854
Absolute Maximum Ratings
Item Supply voltage Input voltage Symbol VDD VIC VI Output voltage *1 Input clamp current Output clamp current Continuous output current Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes: Tstg VO IIK IOK IO Ratings -0.5 to 3.6 -0.5 to 3.6 -0.5 to VDD+0.5 -0.5 to VDD+0.5 -50 -50 50 0.7 -65 to +150 Unit V V V V mA mA mA W C VI < 0 VO < 0 VO = 0 to VDD CLKIN Conditions
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Recommended Operating Conditions
Item Supply voltage Output supply voltage DC input signal voltage High level input voltage High level input voltage Low level input voltage Output differential cross point voltage Output current Input clock slew rate Operating temperature VIH VIH VIL VOX IOH IOL SR Ta Symbol AVDD VDD Min 2.3 2.3 -0.3 1.7 1.7 -0.3 0.5xVDD -0.2 -- -- 1 0 Typ 2.5 2.5 -- -- -- -- -- -- -- -- -- Max 2.7 2.7 VDD+0.3 3.6 VDD+0.3 0.7 0.5xVDD +0.2 -12 12 -- 70 V/ns C Unit Conditions V V V V V V V mA All pins CLKIN FBIN CLKIN, FBIN
Note: Unused inputs must be held high or low to prevent them from floating.
Rev.4, Jan. 2003, page 6 of 11
HD151BF854
Electrical Characteristics
Item Input clamp voltage (All inputs) Output voltage Symbol Min VIK VOH -- Typ *1 -- Max -1.2 -- VDD 0.2 0.6 10 12 300 A mA mA Unit V V Test Conditions II = -18 mA, VDD = 2.3 V IOH = -100 A, VDD = 2.3 to 2.7 V IOH = -12 mA, VDD = 2.3 V IOL = 100 A, VDD = 2.3 to 2.7 V IOL = 12 mA, VDD = 2.3 V VI = 0 V or 2.7 V, VDD = 2.7 V, CLKIN, FBIN VDD = AVDD = 2.7 V, 170 MHz VDD = AVDD = 2.7 V, 170 MHz All Yn, Yn, = open CLKIN and FBIN
VDD-0.2 --
1.7 VOL Input current Analog supply current Dynamic supply current II AICC DICC -- -- -10 -- --
-- -- -- -- -- 250
Input capacitance*2 Delta input capacitance*2
CI CDi
2.5 -0.25
-- --
3.5 0.25
pF pF
Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. 2. Target of design, not 100% tested in production.
Rev.4, Jan. 2003, page 7 of 11
HD151BF854
Switching Characteristics
Ta = 25C, VDD = AVDD = 2.5V
Item Period jitter Half period jitter Cycle to cycle jitter Static phase offset Output clock skew Application clock frequency Slew rate Stabilization time Symbol tPER tHPER tCC tsPE tsk fCLK(A) Min -- -- -- -- -- 60 80 1.0 -- Typ |75| |120| |75| |150| 150 -- 166 -- -- Max -- -- -- -- -- 210 210 2.0 0.1 Unit Test Conditions & Notes ps ps ps ps ps MHz *1, 2 MHz *1, 3 V/ns 20% to 80% ms *6 *4, 5 *7, 8 *8
Operating clock frequency fCLK(O)
Notes: Target of design, not 100% tested in production. 1. The PLL must be able to handle spread spectrum induced skew. (the specification for this frequency modulation can be found in the latest Intel PC100 Registered DIMM specification) 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4. Assumes equal wire length and loading on the clock output and feedback path. 5. Static phase offset does not include jitter. 6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of it's feedback signal to it's reference signal after power on. 7. Period jitter defines the largest variation in clock period, around a nominal clock period. 8. Period jitter and half period jitter are separate specifications that must be met independently of each other.
Rev.4, Jan. 2003, page 8 of 11
HD151BF854
Yn Zo = 60 RT = 120 Yn Zo = 60 C = 14 pF C = 14 pF
*1
*1
Note: 1. SDRAM Cin 3.5 pF x4
Figure 1 Clock outputs test circuit
Yn Yn tcycle n tcycle n+1
t CC = (tcycle n) - (tcycle n+1)
Figure 2 Cycle to cycle jitter
Yx Yx Yy Yy tsk
Figure 3 Output clock skew (Differential clock output)
Rev.4, Jan. 2003, page 9 of 11
HD151BF854
Package Dimensions
Unit : mm
10.2 10.4 Max 28 15
1
14 0.65 1.3 0.13 M 7.9 0.2 0 - 8 0.6 0.15
0.32 0.08 0.30 0.08
5.3
0.22 0.05 0.20 0.05
2.10 Max
0.10
0.1 0.1
Dimension including the plating thickness Base material dimension
SSOP-28 Hitachi Code -- JEDEC -- EIAJ Weight (reference value)
Rev.4, Jan. 2003, page 10 of 11
HD151BF854
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Sales Offices
Hitachi, Ltd.
Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk
Copyright (c) Hitachi, Ltd., 2003. All rights reserved. Printed in Japan.
Colophon 7.0
Rev.4, Jan. 2003, page 11 of 11

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